1. Field of the invention:
An Analog-to-Digital converter (A/D). This invention relates to the sampling of analog wave forms and the measuring of their amplitude at periodic intervals, and generating a binary word to represent the analog amplitude. The binary word may be stored, signal processed by a computer, or transmitted.
2. Description of the prior art:
Heretofore many methods to convert an analog input signal to a digital binary word of n-bits have been used. The problem is, as the number of bits increases, the conversion time increases, reducing the highest frequency that may be sampled. As the number of bits increases, the cost of an analog-to-digital converter increases.
The three most commonly used methods to date are:
(1) SUCCESSIVE APPROXIMATION REGISTER (SAR), a technique where the unknown analog input voltage is compared, one at a time, to the voltages between a series of resistors using analog switches controlled with each clock cycle, by an algorithm. This method requires an 8-bit digital output to have 256 resistors and a maximum of 128 clock cycles to complete one A/D conversion.
The problem with this technique is the number of clock cycles and electronic components increase exponentially with each binary bit added to the binary word. By contrast, the present invention requires at most only one clock cycle to produce a binary word of any number of bits.
(2) BINARY COUNTER is a technique where a binary counter increments with each clock cycle. The binary counter is coupled to a digital-to-analog converter generating a reference voltage. When the reference voltage is equal to the analog input voltage, a comparator changes it's output logic level and stops the incrementing process. The binary word at that point is the output.
The problem with this technique is the number of clock cycles required increases exponentially with each binary bit added to the binary word. With each added bit the time required to make an A/D conversion increases exponentially, reducing the highest frequency that can be converted to a digital binary word. By contrast, the present invention requires at most only one clock cycle to produce a binary word of any number of bits.
(3) FLASH CONVERTERS are a clockless method of converting analog signals to digital binary words using a resistive divider with the number of resistors equal to 2" (n=number of output bits). A separator voltage comparator is coupled to each node of the resistive divider, and the other input of the comparator is coupled to the analog input signal. Logic levels from the comparators' outputs connect to a decimal to BCD (Binary Coded Decimal) decoder where the binary output is taken.
The problem with this technique is that the electronic component count increases exponentially with each binary bit added to the binary word output. This technique requires no clock and is very fast, but the exponential increase in the number of electronic components physically limits the number of binary output bits that can be generated on an integrated circuit. 4,684,924 Class 340/347 AD, by Wood Date: Aug. 4, 1987 TITLE: Analog/Digital Convert Using Remainder Signals
Wood discloses a series summing A/D converter that differs from the present invention in that the analog input signal must travel through every summing circuit regardless of the size of the word or number of binary bits used. This is inherently slower and produces a voltage error with each summing circuit in the analog input signal path. By contrast, the present invention bypasses the summing circuit if the associated bit is not represented in the binary word. This makes the present invention very accurate when converting to digital binary words very small analog voltages that require only the very least significant bits. 4,072,938 Class 340/347 AD, by Buchanan Date: Feb. 7, 1978 TITLE: Bucket Brigade Analog-to-Digital Converter
Buchanan discloses an A/D converter using a charged capacitor, charged by the analog input signal voltage and a reference voltage. The capacitor's charge is the difference of the two potentials. This potential difference is serial shifted to the next less significant bit stage by a clock, where a comparison to the next less significant bit reference voltage is made and then clocked again to the next less significant bit stage and so on. This clocked serial shift method means, to make a 12-bit binary word requires at least 12 clock cycles, instead of only one clock cycle as with the present invention.